The present invention relates to a transistor type ferroelectric memory having a novel structure and a method of manufacturing the same.
As the structure of a related-art one-transistor (1T) type ferroelectric random access memory (FeRAM), a metal-ferroelectric-semiconductor (MFS) structure, a metal-ferroelectric-insulator-semiconductor (MFIS) structure, and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure have been known. However, FeRAMs having any of these structures have many problems.
In the MFS structure, since the surface of a group-IV semiconductor substrate formed of silicon or germanium is easily oxidized, it is very difficult to form an oxide ferroelectric layer on the surface of the substrate. This prevents the MFS structure from being put into practical use. Specifically, when forming the oxide ferroelectric layer on the group-IV semiconductor (e.g. silicon) layer, undesirable film such as a silicon oxide film is formed at the interface between the silicon layer and the oxide ferroelectric layer. Since such a film has a low relative dielectric constant, the operating voltage for causing the polarization reversal of the oxide ferroelectric must be increased. Moreover, since electric charges are injected into the film due to occurrence of a trap level in the film, electric charges due to remanent polarization are defeated, whereby a sufficient polarization reversal does not occur.
The MFIS structure suffers from a problem similar to that of the MFS structure since a silicon oxide layer is generally used as the insulating layer (I layer). Specifically, since silicon oxide has a low relative dielectric constant, the operating voltage for causing the polarization reversal of the oxide ferroelectric must be increased. Moreover, since electric charges are injected into the silicon oxide film due to occurrence of a trap level in the silicon oxide layer, electric charges due to remanent polarization are defeated, whereby a sufficient polarization reversal does not occur. Moreover, since the silicon oxide layer used as the I layer is amorphous, it is very difficult to form an oxide ferroelectric having a crystal structure on the silicon oxide layer.
The MFMIS structure has an advantage over the MFIS structure in terms of formation of the oxide ferroelectric layer, since a metal layer such as a platinum layer having a relatively good affinity to the oxide ferroelectric with respect to crystallinity is formed on the I layer. However, the MFMIS structure suffers from a problem similar to that of the MFIS structure due to the presence of the I layer.
The MFIS structure and the MFMIS structure having the I layer have the following problem as a nonvolatile memory. In the MFIS structure and the MFMIS structure, the oxide ferroelectric layer (F layer) and the I layer (insulating layer) are capacitively coupled. Therefore, when writing data into the F layer by applying a voltage, the applied voltage is distributed to the I layer and the F layer corresponding to the relative dielectric constant and the thickness of each layer, and electric charges are stored corresponding to the applied voltage. The polarization direction of the stored electric charges is the same as the applied voltage direction in the I layer and the F layer. However, when retaining data without applying a voltage, the metal layer (M layer) and the semiconductor layer (S layer) are short-circuited. In this case, since the polarization direction of the F layer is fixed by the remanent polarization, electric charges are induced in the I layer in an amount the same as that of the ferroelectric capacitor formed by the F layer, and the polarization direction of the electric charges is the reverse of that of the ferroelectric capacitor. Therefore, a large depolarization field is applied to the ferroelectric capacitor from the capacitor formed by the I layer. As a result, the polarization direction of the F layer is reversed, whereby the stored data is lost.